The present invention generally relates to the field of design automation and computer-aided design (CAD) of integrated circuits, and more particularly, to a method and system for analyzing the dynamic behavior of an electrical circuit to determine whether a voltage level provided by the power supply network drops below a predetermined voltage level when a predetermined number of electrical elements switch simultaneously.
Today CMOS (Complementary Metal Oxide Semiconductor) circuit technology and its application to synchronous switching digital VLSI (Very Large Scale Integration) that operates at high frequencies and which shows significant current fluctuations imposes serious constraints on the associated power supplies. The reason lies in the semiconductor fabrication. CMOS circuit technology which uses a combination of n and p-doped semiconductors to achieve low power dissipation. Any path through a gate where current flows includes both kinds of transistors (i.e., n and p-type). Since only one type turns on to a stable state, there is hardly any static power dissipation. However, current flows when the gate switches, which normally occurs when charging the parasitic capacitances.
Current fluctuations typically generate noise voltages, i.e., unintentional variations of the voltage level. Because of such fluctuations, the supply voltage level is prone to drop even below a predetermined voltage level necessary for the faultless operation of the circuits comprising the chip or module, which jeopardizes the operation of the entire system. Therefore, one of the major challenges in modern circuit design is to design a reliable power supply system, i.e., one that provides a voltage supply level that stays within a predefined range even under worst case conditions. Thus, the power supply is required to display a minimum amount of noise even when all the gates forming the logic or memory switch simultaneously.
A conventional approach is to built a power supply network which maintains the lowest possible impedance, from DC level up to its highest operational frequency. In such a system, power supply noise is at minimum. To achieve this goal, the designer provides decoupling capacitors, each generating a local capacitance along the power path from the primary power source down to the switching circuits. The closer to the switching circuit high frequency capacitors, i.e., those showing a good high frequency response, the better the provision for high speed current changes. Ultimately, the power supply decoupling capacitors are best distributed at the chip level among the switching circuits. However, tools to simulate the on-chip power distribution are not commonplace today and are very complex. Furthermore, it is hardly possible to use them interactively during chip physical design, because of their complexity.
Accordingly, it is an object of the present invention to provide a method and a system for analyzing the dynamic behavior of an electrical circuit as part of an integrated circuit to determine whether a voltage level provided by the power supplies drops below a predetermined level during operation of the electrical circuit.
It is another object to provide a method and a system for analyzing the dynamic behavior of the electrical circuit to determine that the voltage level provided by the power supply network drops below the predetermined voltage level when a predetermined number of electrical elements switch simultaneously.
The foregoing and other objects are achieved by a method and a system for analyzing the dynamic behavior of electrical circuits as part of an integrated circuit, wherein each electrical circuit includes a plurality of electrical elements and a power supply system. The power supply system is formed by an external voltage source and by a plurality of electrical connections for providing a predetermined supply voltage level U0 to each electrical element. An analysis determines whether the voltage level at any of the electrical elements drops below a predetermined voltage level when a certain number of electrical elements switch simultaneously. In order to calculate a worst case, it is considered that all electrical elements switch from one state into another at the same time.
In a first step, a design data set that represents the technical specifications of the electrical circuit or the integrated circuit, is read in order to extract the location and the value of the switching and non-switching capacitance Cs, C0. Additionally, a circuit and technology specified propagation speed xcexd is provided. In the next step, a length is determined to specify the size of a portion of a circuit area upon which the electrical circuit is formed. Thereafter, the circuit area is divided in a plurality of partitions of a specified size, and the switching capacitance Cs and the non-switching capacitance C0 are separately summarized for each portion. Then, the voltage level drop xcex94U is individually calculated for each partition. Finally, the calculated voltage level drop xcex94U is displayed in relation to the respective partition.
The method of the present invention can be used for on-chip power supply network evaluation. It was found to be sufficiently efficient for early use in the chip development process and the chip physical design phase. Since the method and system measures the power supply integrity, i.e., whether the power supply operation is unimpaired by the circuit operation, it allows optimize the chip layout and power supply decoupling capacitors.
The behavior of a power supply system being a part of an electrical circuit subjected to analysis, as described above, is conditioned by many different electrical values, such as the non-inductive resistance, the capacity reactance and the inductance. However, typically, the power supply networks in question are mainly inductance dominated, i.e., the influence of the inductance on the system behavior is comparably larger so that the other electrical values may even be neglected for the purpose of the analysis, in accordance to the present invention. Every electrical element, being part of the analyzed electrical circuit, provides a certain capacitance. For the analysis, according to the present invention, the capacitance of each electrical element is divided in two different types. The first type is referred to as switching capacitance Cs, i.e., a capacitance which has to be charged whenever the respective electrical element changes its state or switches. The second type is a non-switching capacitance C0 which in not effected by changing the state of the electrical element nor by its switching. The non-switching capacitance C0, however, keeps some electrical charge which may be supplied to the power supply network.
Charging the switching capacitance Cs of an electrical element during switching is a major physical effect which needs external power supply support. Due to the high switching speed, the inductance dominated power supply path mainly controls the behavior of the voltage level provided by the power supply network to the switching electrical elements. Because of this, an external power supply cannot instantly provide sufficient electrical charge demanded by an electrical element in order to charge the switching capacitance Cs. Instead, the electrical charge needed to charge the switching capacitance Cs is at first taken from the non-switching capacitance C0 being situated very closely in relation to the switching location. Hence, only a fraction of the entire non-switching capacitance C0 is available to provide the electrical charge that is needed for a switching event.
Using the law of charge conservation, the initial voltage collapse or voltage level drop DU of the nominal power supply voltage level U0 can generally be calculated as follows:                               Q          0                =                                            C              0                        ·                          U              0                                =                                                                      (                                                            C                      0                                        +                                          C                      S                                                        )                                ·                                  (                                                            U                      0                                        -                                          Δ                      ⁢                                              xe2x80x83                                            ⁢                      U                                                        )                                            →                              Δ                ⁢                                  xe2x80x83                                ⁢                U                                      =                                                            C                  S                                                                      C                    s                                    +                                      C                    0                                                              ·                              U                0                                                                        (        1        )            
In order to use the above formula for analyzing an entire electrical circuit, a suitable value for the non-switching capacitance C0 needs to be determined. Thus, for calculating the expected voltage collapse xcex94U from all non-switching capacitance only such portion is taken into account which shows its effect on the behavior of the voltage level provided to the switching electrical element. To determine whether a particular non-switching capacitance is able to provide an electrical charge to a switching electrical element, the distance from the non-switching capacitance to the switching electrical element and the voltage collapse propagation speed on the (on-chip) power network xcexd needs to be considered.
Alternatively, only a non-switching capacitance within a critical distance D to the switching location can influence (reduce) the voltage collapse. This can be expressed by the reaction time TR in relation to the transition time TS. The reaction time TR is the span of time wherein an electrical charge is expected to arrive at a switching location. The transition time TS is the span of time needed for the switching event to conclude. Under favorable circumstances, an electrical charge should arrive at a switching location at the latest after half the transition time TS has elapsed. However, other specifications may also be suited for the analysis, according to the present invention, e.g., the electrical charge arriving at the switching location at the latest after a third of the transition time TS has elapsed.
The critical distance D can be calculated according to the following formula, wherein requirement is considered that the reaction time TR is less than half the transition time TS. In this time, a burst noise has to travel twice the critical distance D, at the propagation speed xcexd.                               T          R                =                                            2              ·                              D                v                                      ≤                                          T                S                            2                                →                      D            ≤                                          v                ·                Ts                            4                                                          (        2        )            
The values needed to calculate the critical distance D and the initial voltage collapse xcex94U are known from the design of the electrical circuit. The values for the switching and the non-switching capacitance CS and C0 can be extracted from the chip design data set. The power network propagation speed is known from the technology that includes the electrical circuit and physical designs. The transition time of an electrical element is known from the technology specifications, whereas the reaction time TR is predetermined according to the considerations stated previously.
The respective system according to the present invention includes means for determining the length for specifying the size of a portion of a circuit area upon which the electrical circuit is formed; means for dividing the circuit area into a plurality of portions of the specified size, means for separately summarizing the switching capacitance Cs and the non-switching capacitance C0 individually for each portion and means for calculating the voltage level drop xcex94U individually for each portion.
The present invention can be realized in hardware, in software, or in a combination of hardware and software. Any computer systemxe2x80x94or apparatus adapted for carrying out the methods described hereinxe2x80x94is suited for the stated purpose. A typical combination of hardware and software consists of a general purpose computer system with a computer program that, when loaded and executed, controls the computer system such that it carries out the methods described herein. The present invention can also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and whichxe2x80x94when loaded in a computer systemxe2x80x94is able to carry out these methods.
Computer program means or computer program in the present context includes any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following a) conversion to another language, code or notation; b) reproduction in a different material form.